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| geometry process details principal device types mpsa55 mpsa56 gross die per 5 inch wafer 35,100 process CP704V small signal transistors pnp - high current transistor chip process epitaxial planar die size 22 x 22 mils die thickness 7.1 mils base bonding pad area 3.7 x 3.7 mils emitter bonding pad area 4.2 x 4.2 mils top side metalization al - 30,000? back side metalization au - 18,000? www.centralsemi.com r1 (22-march 2010)
process CP704V typical electrical characteristics www.centralsemi.com r1 (22-march 2010) |
Price & Availability of CP704V
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